In a semiconductor device (particularly, a silicon device), higher integration and lower power consumption have been achieved by miniaturization based on the scaling law (Moore's law). The development of the semiconductor device has been advanced at a pace of 4 times per three years. In recent years, the gate length of a MOSFET has been 20 nm or less, which causes a rising cost of a lithography process (soaring cost of a device and a mask set) or physical limits (operating limits and variation limits) of a device size. Therefore, improvement in device performance caused by an approach different from the miniaturization based on the conventional scaling law is required.
In recent years, a three-dimensional technique has been examined as a technique for adding a new function or increasing the number of elements utilizing the upper space of a semiconductor element. Examples of the three-dimensional (3D) technique include a technique of bonding chips together (Chip to Chip) and a technique of bonding device wafers together (Wafer to Wafer).
When one-generation scaling is advanced, device density is doubled. In order to correspond to the doubled device density, hitherto, scaling by lithography was overwhelmingly superior to the formation of a second-layer transistor in cost. Therefore, the three-dimensional formation of the chip (device) having the same function did not become widely used. However, the demand of the three-dimensional formation increases with the stagnation or blunting of miniaturization.
However, yield is fundamentally managed on a wafer level in the production of the semiconductor device. Therefore, when the above-mentioned 3D technique is used, there is a problem that the yield is remarkably reduced whenever a device wafer or a chip is stacked. Particularly, in a device wafer stack type 3D formation process, wafer alignment and the formation process of a penetration electrode having a high aspect are required. However, the 3D formation process was hardly developed on extension of a ULSI process because of the difference of the order of a processing size. In order to join wafers having a thickness of tens of micrometers by a penetration electrode, a via diameter is required to be at least about 2 μm because of the problem of the embeddability of an electrode. Thus, the size of the penetration electrode (penetration via) is greater by one figure than the ULSI process. Therefore, there is a problem that sufficient via density cannot be obtained and the advantage of the 3D formation cannot be sufficiently exhibited in chip performance.
On the other hand, a technique of transferring a silicon thin film (particularly, a single-crystal silicon thin film) to the other substrate from one substrate is known as a so-called “bonding technique”.
A method using an adhesive material (adhesive layer) and a method using no adhesive material (adhesive layer) exist in bonding substrates together.
A method for subjecting the principal surface of a silicon substrate or the surface of a supporting substrate to a surface activation treatment such as a plasma treatment, an ion beam treatment or an ozone treatment to press-bond the substrates is known as a method for bonding substrates together without using an adhesive material. The following method is described as a method for manufacturing a SOI (silicon on insulator) substrate in Patent Literature 1 (JP2007-194349A). The method includes heating the peripheral part of a substrate having a hydrophilized silicon surface to hydrophobize the peripheral part, press-bonding the silicon surface and the hydrophilized silicon surface of the other substrate, and conducting a heat treatment at 800 to 1000° C. In these methods, a surface treatment, a heat treatment and the like before joining are variously devised. However, a heat treatment of about 1000° C. after joining is generally required in order to finally secure adhesive strength. As an approach of bonding silicon substrates together, the following method is described in Non-Patent Literature 1. The method includes irradiating the silicon substrates with an Ar atom beam to activate the silicon surfaces, and bonding the silicon substrates can be bonded together.
A method for heating-adhering substrates using an epoxy, acrylate or silicone resin materials or the like as an adhesive is known as a method using an adhesive material for bonding substrates together.
As an example of the “bonding” technique, the following method is described in Patent Literature 2 (JP2004-140381A). The method includes forming a thin film device layer on a translucent substrate with an intervention of a separation layer made of amorphous silicon, a metal, and the like interposed therebetween, and bonding the thin film device layer and the other substrate together, with an adhesive layer interposed therebetween. The method further includes irradiating the bonded substrates with light from the translucent substrate side to generate delamination (in-layer delamination and interfacial delamination) in the separation layer, and separating the translucent substrate from the other substrate including the thin film device layer with the separation layer as a base point. Thus, the thin film device layer provided on the translucent substrate is transferred to the other substrate.
The following method is described in Patent Literature 3 (JP05-211128A). The method includes delaminating a silicon substrate from a substrate in which the silicon substrate and a supporting substrate (stiffening material) are joined together such that a thin silicon film (a joined surface side portion of a silicon substrate) leaves on the supporting substrate. Specifically, a hydrogen ion is implanted into the bonded surface side of the silicon substrate before bonding. The silicon substrate and the supporting substrate are then bonded together, and the substrates are heated at a temperature exceeding 500° C. The silicon thin film supported by the supporting substrate is delaminated from the silicon substrate by utilizing the evolution of hydrogen bubbles in the silicon substrate by the heating. A method for implanting a hydrogen ion to delaminate (transfer) a silicon thin film is known as Smart-Cut™ method by SOITEC Corporation (or SOITEC method).
As a method for forming a semiconductor crystal film on a substrate without using the “bonding” technique, the following method is described in Patent Literature 4 (JP2005-45036A). The method includes forming an insulating film on a substrate, introducing an impurity element into the insulating film so that a concentration gradient is made in the insulating film, forming a non-single crystal film on the insulating film, and irradiating the non-single crystal film with an energy beam to fuse and solidify the non-single crystal film, thereby crystallizing the non-single crystal film. In the method, a gradual temperature gradient is formed in the surface of the film by the difference in a thermal conductivity according to the concentration gradient of the impurity element, during the irradiation of the energy beam. Thereby, the crystal can be grown in a low crystallization rate, and a good crystal film having great crystal grains can be formed.